Method to prevent static destruction of an active element comprised in a liquid crystal display device

ABSTRACT

A liquid crystal display device which utilizes an active matrix substrate and its substrate, and which is provided with a novel method of manufacture which can reduce the manufacturing process of amorphous silicon thin film transistors of reverse stagger construction, and an electrostatic protection means which is created using this method of manufacture. In a thin film transistor manufacturing process, along with forming an aperture for connecting the contact hole and the external terminal in a manufacturing process for a thin film transistor, utilization is made of ITO film as the wiring. The electrostatic protection means is formed from a bi-directional diode (electrostatic protection element) which is composed utilizing an MOS transistor connected between the electrode (PAD) for connecting the external terminal, and the joint electric potential line. The electrostatic protection element is substantially a transistor, with great current capacity, and utilizing the TFT formation process of pixel components in their existent state, the process can be formed without any complications.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for manufacturing a thin filmelement, an active matrix substrate, a liquid crystal display device andan active matrix substrate, as well as a method for preventing theelectrostatic destruction of an active element included in a liquidcrystal display device.

2. Description of Related Art

With the liquid crystal display device having an active matrix format,the switching element in each pixel electrode is connected, and eachpixel electrode is switched through the switching element. As theswitching element, utilization may be made, for example, of a thin filmtransistor (TFT).

The construction and operation of the thin film transistor isfundamentally the same as the single crystal silicon MOS transistor.

As the structure of the thin film transistor which utilizes amorphoussilicon (α-Si) there are a number of well known types of construction.However, bottom gate structure (reverse stagger structure) wherein thegate electrode is at the bottom of the amorphous silicon film isgenerally used.

In the structure of a thin film transistor, it is important to reducethe number of construction processes and to assure a high yield.

In addition, in the production process of an active matrix substrate, itis important to effectively protect the thin film transistor from thedestruction caused by the generated static electricity. The technologyfor protecting the thin film transistor from electrostatic destructionis disclosed, for example, in Japanese laid open utility model 63-33130which is recorded on microfilm, or in laid open patent publication62-187885.

SUMMARY OF THE INVENTION

One of the objects of the present invention is to provide a novel thinfilm element production process technology which enables the reductionof the number of thin film transistor manufacturing processes, with ahigh degree of reliability.

In addition, another object of the present invention is to provide anactive matrix substrate and a liquid crystal display device in which theproduction process is formed utilizing production process technologywhich is not complicated, and which has adequate electrostaticprevention capacity for the protection elements. In addition, anotherobject of the present invention is to provide an electrostaticdestruction prevention method which can prevent the electrostaticdestruction of the active elements (TFT) included in the TFT substrate.

One of the desirable situations for the production method of thin filmelements according to the present invention is that, at the time ofproducing the thin film elements having a bottom gate construction, itincludes a process for forming a protective film which covers the sourceelectrode, the drain electrode, and the gate electrode material layer.Subsequently a process for forming a first aperture component having apart of a built up film comprising a gate electrode layer is selectivelyetched. A gate insulation film which is present on a gate electrodematerial layer, and a protective film are also formed so that a portionof the surface of the gate electrode layer and the gate electrodematerial layer is exposed. At the same time, a second aperture componentis formed wherein selected etching of a portion of the source electrodelayer and the protective film on the drain electrode layer isaccomplished, so as to expose a part of the source electrode layer andthe surface of the drain electrode layer; and a process whichsubsequently connects at least one of the gate electrode layer, the gateelectrode material layer, the source electrode layer, or the drainelectrode layer with the electrically conductive material layer throughthe first and second aperture.

According to the described thin film element manufacturing method,selective etching of the insulation film is accomplished all at once.Hence, the formation process of an aperture to connect the externalconnection terminal to the electrode (pad open process), and theformation process of an aperture for connecting the internal wiring tothe electrode (contact hole formation process) can be jointlyaccomplished, and the number of processes can be reduced.

As the “electrically conductive material layer”, ITO (indium tin oxide)film is desirably utilized. As described above, the first aperture isformed so that it passes through the overlapped films comprising thefirst insulation film over the gate electrode material layer and thesecond insulation film over the first insulation film, a deep contacthole is created so as to correspond in depth of the two insulationfilms.

However, since ITO has a high melting point, ITO has good step coveragein comparison with aluminum, and the like, therefore the connection isnot poor even if it is accomplished through a deep contact hole.

In addition to the ITO film, other transparent electrode materials whichhave a high melting point, such as metallic oxides can also be utilizedas the “electrically conductive material layer”. For example, metallicoxides such as SnOx and ZnOx may be utilized. In this case as well, thestep coverage is able to withstand actual use.

In addition, with one desirable situation for an active matrix substrateaccording to the present invention, a protective means used to preventthe electrostatic destruction used with thin film transistors isconnected between at least one line between the scanning line and thesignal line, or between an electrically equivalent region to said lineand a joint electric potential line.

The protective means used to prevent electrostatic destruction iscomposed to include a diode which is constructed so as to connect thegate electrode layer in the thin film transistor and the drain electrodelayer, and by selectively removing the insulation layer from the gateelectrode layer to electrically connect the drain electrode and the gateelectrode, and by selectively removing the resultant first aperturecomponent and the insulation from the drained electrode layer. Theresultant second aperture component is formed by the same manufacturingprocess; and furthermore, the gate electrode layer and the drainelectrode layer are connected by the electrically conducted layer formedfrom the same material as the pixel electrodes, through the first andsecond apertures.

Short circuiting the TFT gate and drain, the formed MOS diode (MISdiode) comprises a substantive transistor, in which there is a highcapacity for the flow of electric current, and the static electricitycan be quickly absorbed, with high static electricity protectioncapacity. In addition, since it is substantially a transistor, thecontrol of the electric current/voltage characteristic threshold voltage(V_(th)) can be easily accomplished. Furthermore, it is possible toreduce the unnecessary leakage of electric current. In addition, thenumber of manufacturing processes of the thin film element is reduced,and construction is simplified. As the “pixel electrode” and the“electrically conductive layer formed from the same material as thepixel electrode”, desirable utilization is made of ITO (indium tinoxide) film. Other than the ITO film, utilization may also be made ofother transparent electrode materials having a high melting point, suchas metallic oxides. For example, use may be made of such metallic oxidesas SnOx, and ZnOx and the like.

With one desirable situation for the active matrix substrate accordingto the present invention, the described “line which has at least one ofeither a scanning line or a signal line, and electrically equivalentregions” comprises an electrode (pad) for connecting an externalconnection element, and the “joint electric potential line” with a line(LC-COM line) to which is applied a standard electric potential whichbecomes the standard at the time of the alternating current driving ofthe liquid crystals, or with the manufacturing stage of the liquidcrystal display device, it comprises a line (guard ring) for jointlyconnecting the electrode (pad) for connecting the external connectionelement and making it the same electric potential.

The guard ring is a line connected to the exterior of the pad, andserves as a counter measure for static electricity in the manufacturingstage of the liquid crystal display device. Both the LC-COM line and theguarding ring are joint electric potential lines. Furthermore, byconnecting a protective diode between the pad and these lines, staticelectricity can be avoided in the lines.

In addition, one of the desirable situations for an active matrixsubstrate according to the present invention is that the “protectionmeans used to prevent static electricity destruction” is attached bothbetween the electrode (pad) for connecting an outside terminal and theline (LC-COM line) to which has been applied the standard electricpotential which became the standard at the time of alternate currentdriving of the liquid crystal; as well as between the electrode (pad)for connecting the external terminal and the line (guard ring) forjointly connecting the electrode (pad) for connecting the externalterminal and making it the same electric potential.

The guard ring, following the emulation between the TFT substrate andthe facing substrate (color filter substrate) is completely cut offprior to the connection of the IC used for the drive, and the LC-COMline is the line which remains in the final product. Furthermore, evenafter the substrate cutoff prior to the connection of the IC, accordingto the construction described above, the pixel TFT is protected fromelectrostatic destruction, and continuing, there is an improvement inthe reliability of the product.

In addition, since the protective diode remains even in the finalproduct, there is also an improvement in the strength of the protectionagainst electrostatic destruction at the time of the product's actualuse.

Furthermore, since it is a protective diode which uses the TFT, controlof the threshold value voltage (V_(th)) can be easily accomplished, andsince the current leakage can also be reduced, there is no negativeinfluence even if the diode remains in the final product.

In addition, with one desirable situation for a method of manufacturingan active matrix substrate according to the present invention, theelectrostatic destruction prevention protection means provides abi-directional diode which jointly connects the first diode anode andthe second diode cathode, and jointly connects the first diode cathodeand the second diode anode.

Since it is a bi-direction protective diode, the TFT can be protectedfrom both the positive electrode surge and negative electrode surge.

In addition, the liquid crystal display device is constructed using theactive matrix substrate of the present invention. By assuredlypreventing electrostatic destruction of the active element (TFT) of thepixels in the active matrix substrate, the reliability of the liquidcrystal display device is also improved. In addition, with one desirablesituation of a method of manufacturing an active matrix substrateaccording to the present invention at the time of forming the TFT of thebottom gate construction, in a specified region on the insulation film,at the same time as forming a source/drain electrode layer from the samematerials, it includes a process for forming the source/drain electrodematerial layer from the same material as the source/drain electrodelayer; and a process for creating a protective film which covers thesource/drain electrode layer, and the source/drain electrode layermaterial; and a process for forming a second aperture so as to expose apart of the surface of the source/drain electrode layer or thesource/drain electrode material layer, selectively etching theprotective film on the source/drain electrode layer or the source/drainelectrode material layer, at the same time as forming a first apertureso as to expose a part of the surface of the gate electrode layer andthe gate electrode material layer, selectively etching the film buildupof the gate insulation film which exists on the gate electrode layer andthe gate electrode material layer, as well as the protective film; and aprocess for connecting the electrically conductive material layer to thegate electrode layer, the gate electrode material layer, thesource/drain electrode layer, or the source/drain electrode materiallayer, through the first and second apertures.

According to the described method of manufacture of the thin filmelement, selective etching of the insulation film is accomplished all atonce. Hence, the formation process (pad open process) of the aperturefor connecting the external terminal to the pad, and the formationprocess (contact hole formation process) of the aperture for connectingthe wiring to the electrodes are jointly accomplished, thereby reducingthe number of processes.

This method of manufacturing can also be used in the formation of theMOS diode as the static electricity protection element. In addition,utilization may also be made in the formation of the crossunder wiringin the vicinity of the pad. The “crossunder wiring” at the time ofleading the internal wiring of the liquid crystal display device to theoutside of the seal material achieves the protection of the wiring bymeans of a thick layer of insulating film between them connecting thewiring in the upper layer to the wiring of the lower layer with thewiring being used to lead to the outside in a round about manner.

The “conducted material layer” is desirably the same material as thepixel electrode. By this means, the wiring which is formed of theelectrically conductive material is capable of being formed at the sametime as the process for forming the pixel electrodes.

Furthermore, desirable use is made of ITO (indium tin oxide) film as the“electrically conductive material layer”. Other than ITO film, use mayalso be made of other transparent electrode materials, having a highmelting point such as metallic oxides.

In addition, as a preferable situation for an electrostatic destructionprevention method in the active matrix liquid crystal display deviceaccording to the present invention, a protective means used forelectrostatic destruction prevention formed from a bi-directional diodeis attached between at least one of either the scanning line or thesignal line, or a region which is electrically equivalent to the lineand a joint electric potential line, by which means prevention can beaccomplished of electrostatic destruction of an active element includedin the liquid crystal display device.

The electrostatic destruction of the active element (TFT) included inthe active matrix substrate can be assuredly prevented.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-6 are cross sectional diagrams of the device following eachprocess, and show the construction method of the thin film elementaccording to the present invention.

FIG. 7A-FIG. 7F are drawings which explain the characteristics of themanufacturing process technology shown in FIGS. 1-6.

FIGS. 8A-8G are cross-sectional diagrams of the device following eachprocess of a contrasting example.

FIG. 9 is a diagram which shows a compositional example of the TFTsubstrate according to the present invention.

FIG. 10 is a diagram which shows the composition in the pad periphery ofthe TFT substrate of FIG. 9.

FIG. 11A shows the composition of the electrostatic protection circuit;FIG. 11B shows the equivalent circuit of an electrostatic protectioncircuit; and FIG. 11C is a diagram which shows the electricvoltage/electric current characteristics of an electrostatic protectioncircuit.

FIG. 12 is a diagram which shows the plane surface layout of anelectrostatic protection circuit.

FIG. 13 is a diagram for explaining the composition of an electrostaticprotection circuit of FIG. 12, using cross-sectional construction of thedevice.

FIG. 14 is a diagram for explaining the function of the electrostaticprotection circuit.

FIG. 15 is a diagram which shows a sample structure when the wiring ofthe liquid crystal panel is led to the bonding pad.

FIG. 16 is a diagram which shows an example of the location for ITO usein a region which excludes the pixels in an active matrix substrateaccording to the present invention.

FIG. 17 is a diagram which shows the plane surface layout form of thepixels in the liquid crystal display device according to the presentinvention.

FIG. 18 is a diagram which shows a cross-section of the liquid crystaldisplay device along the line B-B of FIG. 17.

FIGS. 19-25 are respective cross-sectional diagrams of the devicefollowing each process which shows the method of construction of anactive matrix substrate according to the present invention.

FIG. 26 is a diagram which shows the cross-sectional structure of theessential components of the liquid crystal display device in itsassembled form utilizing the active matrix substrate of FIG. 25.

FIG. 27 is a diagram for explaining the dividing process of thesubstrate by means of a cell division device.

FIG. 28 is a diagram for explaining a summary of the entire constructionof the liquid crystal display device of an active matrix type.

FIG. 29 is a circuit diagram which shows the composition of the pixelcomponents of the liquid crystal display device of an active matrixtype.

FIG. 30 is a diagram which shows the voltage wave form for driving theliquid crystal in the pixel component of FIG. 29.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

An explanation is provided hereafter of the form of the execution of thepresent invention, with reference to the drawings.

First Embodiment

FIGS. 1-6 are cross-sectional diagrams of the device following eachprocess which show an example of the construction method of the thinfilm element (bottom gate construction TFT) of the present invention.

Contents of each manufacturing process

Process 1

As shown in FIG. 1, using photolithography technology on the glasssubstrate (non-alkali substrate) 2, formation can be accomplished forexample of gate electrode 4a formed from Cr (chrome) which has athickness of 1,300 Å approximately, and gate electrode material layers4b and 4c. The gate electrode 4a is a gate electrode of the TFT of abottom gate construction formed in a matrix shape on the pixel. Inaddition, the gate electrode material 4b becomes the region formed bythe protective element used to prevent electrostatic destruction,described hereafter. In addition, the gate electrode material layer 4cbecomes the region formed for use in connections with externalcomponents, or for the elements used for scanning.

Next, by means of a plasma CVD method, continuous formation isaccomplished by amorphous silicon film 8 in which there are no dopedimpurities, as well as the n type silicon film ((ohmic-phonetic) contactlayer) 10; and next, by means of photo-etching, islands can be createdof amorphous silicon film 8 and n type silicon film (ohmic contactlayer) 10.

In this instance, the thickness of the gate insulation film 6 is forexample 3000 Å approximately, and the thickness of the genuine siliconfilm 8 is for example approximately 3000 Å, and the thickness of theohmic contact layer 10 is for example approximately 500 Å.

With this process, characteristically there is no formation of a contacthole relative to the gate insulation film.

Process 2

Next, as shown in FIG. 2 for example, formation is accomplished by meansof sputtering and photo-etching the source/drain electrodes 12a and 12bof approximately 1300 Å formed from Cr (chrome).

Process 3

Next, as shown in FIG. 3, utilization is made of the source/drainelectrodes 12a and 12b as the mask, and the central portion of the ohmiccontact layer 10 is removed by etching, and separation (separationetching) is accomplished on the source/drain. In this instance, etchingis accomplished for the purpose of patterning the source/drainelectrodes and separation etching can be continuously accomplishedwithin the same chamber of the same etching device.

In other words, first of all etching of the source/drain electrodes 12a,12b is accomplished using etching gas of the Cl₂ type. Continuing,etching of the center portion of the ohmic contact layer 10 can beaccomplished by switching to gas of the SF₆ type for the etching gas.

Process 4

Next, as shown in FIG. 4, formation of the protective film 14 isaccomplished, for example, by means of the plasma CVD method. Theprotective film 14 is for example a silicon nitride film (SiN_(x)) ofapproximately 2,000 Å.

Process 5

Next, as shown in FIG. 5, contact holes 16, and 18 are formed on aportion of the protective film 14, at the same time as aperture 20 isformed for connecting to the outside terminal (bonding wire or IC outerlead).

The aperture 20 and contact hole 18 are formed so as to pass through thebuilt up film comprising the gate insulation film 6 and the protectivefilm 14. The contact hole 16 is formed so as to only pass through theprotective film 14.

When forming the aperture 20 and the contact hole 18, the gate electrodematerial layer 4b and 4c respectively function as etching stoppers. Inaddition, when forming the contact hole 16, the source/drain electrode12b functions as an etching stopper.

Process 6

Next, as shown in FIG. 6, ITO (indium tin oxide) film is deposited witha thickness of approximately 500 Å, accomplishing selective etching, andforming wiring 22a and the electrode 22b from the ITO. The etching ofthe ITO is accomplished by means of wet etching in which utilization ismade of a compound liquid of HCl/HNO₃/H₂O. As explained, the aperture 20and the contact hole 18 are formed to pass through the built up filmcomposed of the gate insulation film 6 and the protective film 14.Furthermore, this becomes a contact hole with a depth corresponding tothe thickness of the two layer insulation film.

However, since the ITO has a high melting point, the step coverage isgood in comparison to aluminum and the like. Furthermore, there is not apoor connection even though the contact hole may be deep. Moreover,other than ITO, utilization may also be made of other transparentelectrode materials having a high melting point such as metallic oxide.For example, utilization may be made of metallic oxides such as SnOx andZnOx. In this case as well, the step coverage is able to also withstandactual application.

The TFT having bottom gate construction which is produced in this manneris used as a pixel switching element in an active matrix substrate. Inaddition, the electrode 22b formed from the ITO becomes a pad forconnecting the external terminal (IC outer lead and the like).

Characteristics of the Present Manufacturing Method

FIGS. 7A-7F show the manufacturing process of the TFT applied to thestate of the present embodiment recorded in FIG. 1 through FIG. 6. Onthe other hand, FIGS. 8A-8G show the manufacturing process of the TFT ina contrast example. This contrast example was considered by the presentinventors to clarify the characteristics of the manufacturing process ofthe TFT applied to the shape of the present embodiment, and is not aprior art example.

FIG. 8A of the contrast example is the same as FIG. 7A. In FIGS. 8A-8G,the same reference numbers are applied to the same components as inFIGS. 7A-F.

In the case of the contrast example, as shown in FIG. 8B, prior to thecreation of the drain electrode layer, the contact holes K1, and K2 areformed.

Also, as shown in FIG. 8C, formation is accomplished of the source/drainelectrode layers 12a and 12b, as well as the source/drain electrodematerial layers 12c, and 12d formed from the same materials. Next,formation of the ITO film 30 is accomplished as shown in FIG. 8D.Subsequently, etching (separation etching) is accomplished of the centerportion of the ohmic layer 10 as shown in FIG. 8E. Subsequently,formation of the protective film 40 is accomplished as shown in FIG. 8F.

Finally, formation of the aperture K3 is accomplished as shown in FIG.8G. By this means, the surface of the source/drain electrode materiallayer 12d is exposed, and the electrode (pad) is formed for the purposeof connecting the external connection terminal.

According to the manufacturing method of this type of contrast example,in the formation process of the contact hole in FIG. 8B, a process isadded to form the aperture K3 in FIG. 8G, with the necessity of a totalof two aperture formation processes.

In this regard, according to the manufacturing method of the presentembodiment, as shown in FIG. 7E, formation is accomplished of apertures16, 18, and 20 all at once. In other words, at the same time as formingthe aperture passing through the built up film comprising the protectivefilm 14 and the gate insulation film 6, through the simultaneouspatterning also of the protective film 14 on the source/drain electrodelayer 12b, the aperture formation process may be accomplished at onetime. Furthermore, the light exposure process can be reduced by oneprocess. In accompaniment with this, the process of depositing the photoresist film, and its etching process becomes unnecessary. Furthermore,altogether there is a reduction of three processes. In other words, themanufacturing process is simplified.

In addition, according to the manufacturing method of the presentembodiment, patterning (dry etching) of the source/drain electrode 12aand 12b are continued as shown in FIG. 7b and the etching (dry etching)of the center part of the ohmic contact layer 10 shown in FIG. 7C iscontinued, and is accomplished within the same chamber. In other words,by chronologically switching the etching gas within the same chamber, itis possible for etching to be continued.

In this regard, in the case of the contrast example, following thepatterning (dry etching) of the source/drain electrode layers 12a and12b of FIG. 8C, wet quenching is accomplished of the ITO film 30 of FIG.8D, and subsequently, the etching (dry etching) is accomplished of thecenter portion of the ohmic layer 10 of FIG. 8E. The ITO film cannot beprocessed by means of dry etching, and since there is no accomplishmentof processing by means of wet etching, each of the etching processesshown in FIGS. 8C, 8D, and 8E, cannot be continuously accomplishedwithin a single chamber. Hence, it becomes necessary for the substrateto be handled following each process, making the operation inconvenient.

In addition, in the case of the shape of the present embodiment, theprotective film 14 is necessarily present between the ITO films 22a and22b, and the source/drain electrodes 12a, 12b. This being the case, inthe other regions (not shown in the drawing) of the substrate, it meansthat the wiring formed from the ITO film, and the wiring or electrodesformed from the same material as the source/drain electrodes areassuredly and electrically separated.

However, in the case of the contrast example, the ITO film 30 and thesource/drain electrodes 10a, 10b belong in the same layer. In otherwords, both are laminated, and no protective layer is present betweenthe two. Hence, in other regions (not shown in the diagram) of thesubstrate, if foreign matter is present, then notwithstanding the factthat they must be insulated thereafter, there is the concern that wiringformed from the ITO film, and wiring or electrodes formed from the samematerial as the source/drain electrodes will become completely shorted.In other words, the device formed by the method of manufacture of thepresent embodiment has high reliability.

In addition, with the contrast example, in order to form (in FIG. 8D)the ITO film 30 by means of a relatively fast step, in the subsequentprocesses, there is some concern of staining by means of indium (In) ortin (Sn) comprising the ITO composite product.

In this regard, with the method of manufacture according to the presentembodiment, since the ITO film 22a and 22b is formed in the finalprocess, there is little concern of staining being caused by the tin(Sn) comprising the ITO composite.

In this manner, according to the method of manufacture of the presentembodiment, the manufacturing process can be shortened, and a device canbe manufactured having high reliability.

Second Embodiment

Next, an explanation of the second embodiment of the present inventionis provided hereafter with reference to FIGS. 9 through 18.

FIG. 9 is a diagram which shows the plane surface layout of an activematrix substrate in which application is made of the second embodimentof the present invention.

The active matrix substrate of FIG. 9 is utilized in a liquid crystaldisplay device. As the protective elements used as switching elementsfor the pixels, and used to prevent electrostatic destruction,utilization is made of TFT manufactured by the manufacturing methodexplained in the first embodiment.

The pixel parts 4000 (in the diagram shown by the dotted line) areformed from multiple pixles 120, and each pixel is composed to includeTFT (switching element) 3000. The TFT 3000 is attached to theintersecting points of the scanning line 52 and the signal line 54.

To each end of the signal line 54 and the scanning line 52 isrespectively attached a pad 160A, and 160B, with the first protectiveelement 140A and 140B being connected between the pad and the LC-COMline 180, with a second protective element 150A, and 150B being formedbetween the pad and the guard ring 100. Furthermore, the LC-COM line 180is also connected to the facing electrode through the silver point pad110.

“Pads 160A and 160B” are electrodes for connecting the bonding wire orthe (bump-phonetic) electrode or for connecting electrodes (externalterminals) which use polyimide tape.

In addition, the “LC-COM line 180” is a line to which an electricpotential is applied which becomes the standard liquid crystal drive.The common electric potential LC-COM, for example, as shown in FIG. 30is established to the electric potential which is reduced only DV bymeans of the midpoint electric potential V_(B) of the display signalvoltage V_(X). In other words, as shown in the example in FIG. 29, inthe pixel TFT 3000, a capacity C_(GS) is present between thegate/source, and with its influence, between the display signal voltageV_(X) and the final maintained voltage V_(S) is produced the voltagepotential difference DV. In order to compensate for the electricpotential difference DV, the electric potential reduced by only DVbecomes the joint standard electric potential by means of the midpointelectric potential V_(B) of the display signal voltage V_(X).

Furthermore, in FIG. 29, X represents the signal line, and Y representsthe scanning line, C_(LC) shows the equivalent capacity of the liquidcrystal, and the C_(ad) shows the maintenance capacity. In addition, inFIG. 30, V_(X) represents the displayed signal voltage which is suppliedto the signal line X, and V is the scanning signal voltage supplied tothe scanning line Y.

In addition, the guard ring 100 is a line which is attached to theoutside of the pads 160A and 160B as an electrostatic countermeasure tothe manufacturing stage of the liquid crystal display device.

Both the LC-COM line 180 and the guard ring 100 are joint electricpotential lines, and continuing, the electrostatic electricity avoidsthese lines by the connection of a protective diode between the pad andthese lines.

In addition, the guard ring 100, as shown in FIG. 27, following theemulation of the TFT substrate 1300 and the opposing substrate (colorfilter substrate), completely cuts off along the scribe line (SB) priorto the connection of the IC for drive use, however, the LC-COM line 180is a line which remains in the final product. Furthermore, following thesubstrate cutoff, even prior to the connection of the IC, the TFT of thepixel components are protected from electrostatic destruction by meansof the first protective element 140, and continuing, there is improvedreliability of the product.

In addition, since the protective diode also remains in the finalproduct, there is also an improvement in the electrostatic destructiveprotection strength in the actually used final product.

Furthermore, since the protective diode utilizes the TFT, the control ofthe threshold value voltage (V_(th)) is easy, and since the amount ofleaking electric current can also be reduced, there is no negativeinfluence even if the diode remains in the final product.

A practical embodiment of the protection elements is shown in FIGS.11A-11C.

In other words, as shown in FIG. 11A, the protective element connectsthe MOS diode formed from the connection of the gate/drain of the firstTFT (F1), and the MOS diode formed by connecting the gate/drain of thesecond TFT (F2) mutually in the reverse direction, in parallel. Theequivalent circuit is such as that which is shown in FIG. 11B.

Furthermore, as shown in FIG. 11C, the protective element has nonlinearshape characteristics in both directions, in terms of the electriccurrent/electric voltage characteristics. Each diode is given a highimpedance at the time of low voltage impression, becoming a lowimpedance state at the time of high voltage impression. In addition,each diode is substantially a transistor, and the electric current flowcapacity is great, and since the static electricity can be quicklyabsorbed, the static electric protective performance is high.

FIG. 10 shows a practical arrangement of the static electricityprotective elements in the periphery of the pads 160A and 160B of FIG.9.

The protective element 140A of FIG. 1 is constructed by means of thinfilm transistors M60 and M62 which are connected between the gate/drain,and in the same manner, the protective element 140B of FIG. 1 is formedfrom the thin film transistors M40 and M42.

In the same manner, both the second protective elements 150A and 150Bare formed from the thin film transistors M80, M82, M20, and M22.

These protective elements are turned on when there is the impression ofa excessive positive or negative surge, and there is movement so thatthe LC-COM line 180 or the guard ring 100 avoid the surge. In addition,a second protective element 150 arranged on the other side of the pad isadded to the function of the electrostatic protection, and each of thepads 160 are shorted by the guard ring 100, with the function ofpreventing a final scan from becoming impossible in the array process.An explanation of this is provided hereafter with reference to FIG. 14.

As shown in FIG. 14, a case where the probe of the array tester 200(which has 220 amp) is connected to the pad 160A1 to test the pixel TFT(Ma) is considered.

At this time, the second protective element 150A1 and the secondprotective element 150A2 maintain a state of high impedance, andfurthermore the pixels TFT (Ma) and TFT (Mb)are electrically separated.Hence, crosstalk with other transistors is prevented, andexperimentation can be accomplished only relative to the specified TFT(Ma).

In addition, as shown in FIG. 27, when the creation of the TFT substrate1300 is complete, then following the completion of each of the processescomprising the coating of the facing film, the rubbing process, thecoating process of the seal material (spacer), the substrate emulationprocess, the dividing process, and the liquid crystal injection and sealprevention process, then prior to the connection of the IC used for thedrive, by cutting off along the scribe line (SB), the guard ring 100 iscompletely removed.

However, since the first protective element 140 connected between theLC-COM line 180 and the pad 160 is present, then even prior to theconnection of the IC used as the drive, electrostatic protection isaccomplished.

Furthermore, the first protective element also remains in the finalproduct, however, with the protective element which uses TFT in order toaccomplish positive threshold control, there is no concern of reducingthe reliability of the product by means of the leakage of electriccurrent and the like.

Next, an explanation is provided on the construction of the device ofthe first and second transistors (F1, F2) shown in FIG. 11A, withreference to FIG. 12 and FIG. 13.

With the present embodiment, as shown in FIG. 12, the film (ITO film)300, 320, and 330 formed from the ITO comprising the pixel electrodematerial is used as the wiring used to connect the gate/drain.

The cross-sectional construction corresponding to each components(A)-(F) in the plane layout of FIG. 4 is shown in FIG. 13.

As shown in the figure, the first thin film transistor F1 and the secondthin film transistor F2 which compose the static electricity protectionelement are both provided with a reverse stagger construction (bottomgate construction).

In other words, formation of gate electrode layer 410, 420, 430, and 440is accomplished on the glass substrate 400, formation of a gateinsulation film 450 being accomplished on it, forming genuine amorphoussilicon layers 470, and 472, and forming a drain electrode (sourceelectrode) layer 492 through the n type ohmic layer 480, a protectivelayer 460 being formed so as to cover each of these layers. Also,connections are established between the gate/drain by means of the films(ITO films) 300, 320, and 330 formed from the IPO which comprises thepixel electrode material.

The ITO films 300, 320, and 330 connect the gate electrode layer and thedrain electrode layer through the contact hole which passes through thetwo films of the gate insulation film 450 on the gate electrode layer,and the protective film 460; and through the contact hole which passesthrough the protective film 460 on the drain electrode layer 490.

In this case, the ITO has superior step coverage at high melting pointsin comparison with those held by aluminum and the like, owing to whichgood contact is assured even through a deep contact hole passing throughthe two film layers.

In addition, as explained in the first embodiment, the contact holerelative to the gate/source is formed at the same time in the process offorming the aperture (pad open) for connecting the external connectionterminal, thereby shortening the number of processes.

Above, an explanation has been provided with respect to an example forforming the protective diode using the ITO film as wiring. However, theuse of the ITO film as wiring is not limited to this, and for example itis possible for utilization to also be made of a format such as thatshown in FIG. 15.

In other words, in FIG. 15, the ITO film 342 is used in the formation ofthe cross under wiring 342 in the vicinity of the pad 160.

The “cross under wiring” at the time of leading the inner wiring of theliquid display device towards the outside of the seal material 520, inorder to achieve protection of the wiring by means of a thick insulationfilm between the layers, connects the wiring of the upper layer to thewiring of the lower layer, and comprises wiring which is utilized toconduct round about to the outside.

In other words, the ITO film 342 connects the drain electrode layer 490and the layer (gate electrode material layer) 412 which is formed fromthe same material as the gate electrode. By this means, the componentsled to the outside of the gate electrode material layer 412 areprotected in both directions by the gate insulation film 450 and theprotective film 460, improving reliability.

Furthermore, in FIG. 15, the reference numbers 500 and 502 shows facingfilm arrangement, 520 shows the seal material, 540 shows the opposingelectrodes, 562 shows the glass substrate, and 140 shows the liquidcrystal. In addition, connection of the bonding wire 600 isaccomplished, for example, on the pad 160. In substitution for thebonding wire, there are also cases when connection is accomplished ofthe electrode layers utilizing the (bump-phonetic) electrode or thepolyimide film.

The ITO film may also be used as wiring in various other locations. FIG.16 shows an easily understood example of locations in which utilizationof the ITO film may be used as wiring.

In FIG. 16, the ITO film is shown as a fat solid line.

The ITO film in the locations A1-A3 is utilized as wiring for theformation of the protective element, and in location A4, the ITO film isutilized as wiring for connecting the scanning line 52 and the pad 160B,and in location A5, the ITO film is used as the cross-under wiring shownin FIG. 15.

In addition, in location A6, the ITO film is used as wiring forconnecting the horizontal LC-COM line and the perpendicular LC-COM line.In other words, the horizontal LC-COM line is formed from a gatematerial, and the perpendicular LC-COM line is formed from a sourcematerial, owing to which it is necessary for both to be connected by theITO.

Furthermore, in location A6 in FIG. 16, the silver point pad 110 may beformed as a unit by means of the same process as one of either thehorizontal LC-COM line or the perpendicular LC-COM line, and when thusformed, connection of the silver point pad 110 and the LC-COM line(either the horizontal or perpendicular line) not formed in a unit maybe accomplished through the silver pad 110 and the ITO.

Next, an explanation is provided with regard to the construction of eachpixel of the pixel components, with reference to FIGS. 17 and 18.

FIG. 17 shows a plane surface layout of the pixel component.

The TFT (constructed so as to include a gate electrode 720, a drainelectrode 740, and a genuine amorphous silicon layer 475 in which noimpurities are doped) is arranged to function as a switching element andis connected to the scanning line 52 and the signal line 54. The pixelelectrode (ITO) 340 is connected to the drain electrode 740. In thedigram, K2 represents the contact hole, and C_(ad) shows the maintenancecapacity. The maintenance capacity C_(ad) is composed from a buildup ofproximate gate wiring and extended pixel electrodes.

FIG. 18 is a diagram which shows the cross-sectional construction alongthe line B-B in FIG. 17. The cross-sectional construction is the same asthe structure described in FIG. 15.

Third Embodiment

An explanation is provided hereafter with regard to the method ofmanufacture of the TFT substrate applied in the second embodimentdescribed above, with reference to FIGS. 19-26.

In each diagram, the left side is a region in which the switchingtransistor of the pixel element is formed, and the center region is theregion in which the protective element is formed, and the right region(pad component) is where the external connection terminal is connected.

(1) As shown in FIG. 19, first of all, utilization is made of photolithography technology on the glass (non-alkali substrate) substrate400. For example, formed are the electrodes 720, 722, 900, 902, 904which are formed from Cr (chrome) having a thickness of about 1800 Å.

The Cr deposit is accomplished with a reduced pressure of 50 mM Torrutilizing a magnetron sputter device. In addition, the Cr process isaccomplished by means of dry etching in which utilization is made of Cl₂type gas.

Reference numbers 720, 900 are layers (gate electrode layers) whichbecome TFT gate electrodes, wherein reference number 722 is a layerwhich corresponds to the scanning line 52 shown in FIG. 17. In addition,reference numbers 902, and 904 are layers (gate electrode materiallayers) which are formed from the same material as the gate electrodelayer.

(2) Next, as shown in FIG. 20, continuous formation of the gateinsulation film 910 (formed from silicon nitride film SiN_(x) and thelike, formed by plasma CVD method, and genuine amorphous silicon filmwhich does not include doped impurities, and the n type silicon film(ohmic layer) is accomplished. Continuing, patterning of the genuineamorphous silicon film and the n type silicon film (ohmic layer) isaccomplished by means of dry etching in which utilization is made of SF₆type etching gas.

By this means, formation of the genuine amorphous silicon layers 475into islands, and n type silicon layers (ohmic layer) 477, and 922 isaccomplished.

The thickness of the gate insulation film 910 is, for example,approximately 4000 Å, and the thickness of the genuine silicon layers475 and 920 are, for example, approximately 3000 Å, whereas thethickness of the ohmic layers 477 and 922 are, for example, about 900 Å.

With regard to this process, characteristically, there is no formationof a contact hole relative to the gate insulation film. Furthermore, thecoating process of the photo resist, the light exposure process, and theetching removal process comprising three processes become unnecessary,and the number of processes is abbreviated.

(3) Next, as shown in FIG. 21, the source/drain electrode layers 740a,740b, 930a, and 930b which are approximately 1500 Å and which are formedfrom Cr (chrome) are formed by means of sputtering and photo etching.

(4) Continuing, separation of the source and drain, removing the ohmiclayer 477 and 922 center portions by means of etching is accomplishedusing the source/drain electrode layers 740a, 740b, 930a, and 930b as amask.

The source/drain electrode layer patterning shown in FIG. 21, and thesource/drain separation etching shown in FIG. 22 are continuouslyaccomplished within the same dry etching device chamber. In other words,initially, processing of the source/drain electrode layers 740a, 740b,930a, and 930b is accomplished by means of Cl₂ type etching gas.Continuing, by switching the etching gas to the SF₆ type gas, etching ofthe center of the ohmic layers 477, and 922 is accomplished. In thismanner, dry etching is continued in its use, thereby simplifying themanufacturing operation.

(5) Next, as shown in FIG. 23, the protective film 940 is formed usingthe plasma CVD method. This protective film is, for example, a siliconnitride film SiN_(x) having a thickness of approximately 2000 Å.

(6) Next, as shown in FIG. 24, the protective film 940 is selectivelyetched using the SF₆ type etching gas is accomplished. In other words,at the same time as forming the aperture 160 of the pad, formation ofthe contact hole CP1 and the contact hole K8 and K10 is accomplished.

The aperture 160 and the contact hole CP1 are apertures formed throughthe built up film of the gate insulation film 910 and the protectivefilm 940, and the contact holes K8 and K10 are apertures which only passthrough the protective film 940.

In this instance, the gate electrode material layers 902 and 904respectively function as etching stoppers at the time of forming thecontact hole CP1 and the aperture 160, and the source/drain electrodes740a and 930b respectively function as etching stoppers at the time offorming the contact holes K8 and K10.

(7) Next, as shown in FIG. 25, the ITO (indium tin oxide) film isdeposited with a thickness of approximately 500 Å utilizing a magnetronsputtering device), wherein etching is accomplished utilizing a compoundliquid comprising Hcl/HNO₃/H₂O, being processed into a specific pattern.By this means, the active matrix substrate is complete. In FIG. 25, thereference number 950 is a pixel electrode formed from ITO, the referencenumber 952 is wiring formed from ITO which composes a part of theprotective diode, and reference number 954 is an electrode (pad) formedfrom an ITO for connecting the external terminal.

Since ITO having good step coverage is used as wiring, a good electricalconnection can be assumed. As the pixel electrode material, utilizationcan be made also of other transparent electrode materials having a highmelting point, such as metallic oxides. For example, use may be made ofsuch metallic oxides as SnOx and ZnOx and the like.

In addition, as is clear from FIG. 25, a protective film 940 necessarilypasses between the ITO layers 950 and 952, and the source/drainelectrodes 740a, 740b, 930a and 930b. This means that in a wiring region(not shown in the diagram) on the substrate, the wiring layer formedfrom ITO and the source/drain electrode layer are assuredly electricallyseparated. Furthermore, there is no concern of shorting of two itemsbeing caused by foreign substances.

In addition, with this manufacturing method, since the ITO film isformed in the final process (FIG. 25), there is little concern relatingto starting caused by ITO composites such as tin (Sn) and indium (In).In this manner, according to the manufacturing method of the presentembodiment, the manufacturing process of an active matrix substrate canbe abbreviated. Furthermore, it is possible to mount a thin film circuithaving high reliability as an adequate countermeasure for staticelectricity.

Furthermore, in FIG. 25, direct connection of ITO film 952 and 954 tothe gate electrode layer 902 and to the gate electrode material layer904 is accomplished. However, it is also possible for connection to beaccomplished through other materials through buffer layers such asmolybdenum (MO), tantalum (Ta), and titan (Ti) and the like.

Next, an explanation is provided with regard to the process forassembling a liquid crystal display device using a completed activematrix substrate.

As shown in FIG. 28, emulation of the opposing substrate 1500 and theTFT substrate 1300 is accomplished, and, following the cell divisionprocess shown in FIG. 27, enclosure of the liquid crystal isaccomplished. Next, the IC used for the drive is connected, andfurthermore as shown in FIG. 28, the assembly process using polarizedlight plates 1200, and 1600 and the back light 1000 and the like isaccomplished, thereby completing the active matrix liquid crystaldisplay device.

FIG. 26 is a cross-sectional diagram of the essential components of anactive matrix liquid crystal display device. In FIG. 26, the samereference numbers are applied to the same locations as for the drawingsshown in FIGS. 15 and 18.

In FIG. 26, regions are formed wherein the left side is an activematrix, and the center is a protective element (static electricityprotective diode), and the right side is a pad. In the pad, an outerlead 5200 of the driver IC 5500 of the liquid crystal is connectedthrough the anistropic conductive film 5000 on the electrode (pad) 954formed from the ITO. The reference number 5200 is an electricallyconductive granule, the reference 5300 is a film tape, and the referencenumber 5400 is a resin used for encapsulation.

In FIG. 26, adoption is made of the format (TAB) which uses a tapecarrier as the method for connecting the driver-IC. However, otherformats such as the COG (chip on glass) format may also be adopted.

The present invention is not limited to the above embodiment, and it isalso possible to use an appropriate changed form as well where adoptionis made of a positive stagger method TFT. In addition, as the pixelelectrode material, utilization may also be made of other transparentelectrode materials having a high melting point, such as metallicoxides, for the ITO. For example, utilization may be made of metallicoxides such as SnOx and ZnOx and the like. In this instance as well, thestep coverage can withstand actual use.

If the liquid crystal display device of the present embodiment is usedas a display device in a mechanism such as a personal computer, thevalue of the product is improved.

What is claimed is:
 1. A method of manufacturing a thin film element comprising the steps of: (A) forming a gate electrode layer, and a gate electrode material layer on a substrate having the same material as the gate electrode layer; (B) forming a gate insulation film on said gate electrode layer and gate electrode material layer; (C) forming a channel layer and an ohmic contact layer on said gate insulation film that overlaps horizontally with said gate electrode layer; (D) forming a source electrode layer and a drain electrode layer that are connected to said ohmic contact layer; (E) removing said ohmic contact layer from a region between said source electrode layer and the drain electrode layer by etching; (F) forming a protective film for covering said source electrode layer said drain electrode layer and said gate electrode material layer; (G) forming a first aperture wherein a part of said gate insulation film and the overlapping layer of the protective film and said gate electrode material layer are selectively etched for exposing a portion of a surface of one of the gate electrode layer and the gate electrode material layer and at the same times, forming a second aperture wherein a portion of the protective film on the source electrode layer and the drain electrode layer are selectively etched for exposing a portion of a surface of one of the source electrode layer and the drain electrode layer; and (H) connecting an electrically conductive material layer through said first aperture and said second aperture to at least one of the gate electrode layer, the gate electrode material layer, the source electrode layer, and/or the drain electrode layer.
 2. The method of manufacturing a thin film element in claim 1, wherein said first aperture formed in said step (G) is one of a contact aperture for connecting a wiring to said gate electrode material layer, and an aperture for connecting an external terminal to said gate electrode material layer.
 3. The method of manufacturing a thin film element in claim 1, wherein said electrically conductive material is formed of ITO (indium tin oxide).
 4. An active matrix substrate comprising: a thin film transistor (TFT) connected to a scanning line, a signal line arranged in a matrix state, and a pixel electrode to compose pixel components; protective means for preventing static electricity destruction using thin film transistors established between at least one of said scanning line and said signal line, or a region electrically equivalent to the at least one of said scanning line and said signal line, and a common electric potential region, said protective means for preventing electrostatic destruction includes a diode wherein a gate electrode layer in the thin film transistor and a source/drain electrode layer are connected; and a first aperture formed by selectively removing an insulation layer on said gate electrode layer and a second aperture formed in a same manufacturing process by selectively removing an insulating layer on said source/drain electrode layer, said gate electrode layer and said source/drain electrode layer electrically connected via said first aperture and said second aperture by an electrically conductive material layer composed of the same material as said pixel electrode.
 5. The active matrix substrate in claim 4, wherein said first aperture passes through the an overlapping film of the layer that includes a first insulation film on the a gate electrode material layer and passes through the a second insulation film on the first insulation film, and the second aperture passes through only the second insulation film on the source/drain electrode layer.
 6. The active matrix substrate in claim 4, wherein said pixel electrode and the electrically conductive material layer are formed from ITO (indium tin oxide).
 7. The active matrix substrate in claim 4, wherein a region electrically equivalent to at least one of the scanning line and the signal line is an electrode for connecting the an external terminal, and one of a common electric potential line which applies a standard potential that becomes the standard potential at a time of driving the a liquid crystal using alternate current, and a joint electric potential line for commonly connecting the electrode to make the electrode and the one of the common electric potential line and the joint electric potential line the same electric potential.
 8. The active matrix substrate in claim 7, wherein the protective means for preventing electrostatic destruction is provided both between the electrode for connecting the external terminal and the common electric potential line and between the electrode for connecting the external terminal and the joint electric potential line.
 9. The active matrix substrate in claim 4, wherein said protective means for preventing static electricity destruction includes a bi-directional diode for commonly connecting a first diode anode and a second diode cathode, for commonly connecting a first diode cathode and a second diode anode.
 10. A liquid crystal display device using the active matrix substrate described in claim
 4. 11. A method of manufacturing an active matrix substrate comprising the steps of: (A) forming a gate electrode layer, and a gate electrode material layer on a substrate having the same material as the gate electrode layer; (B) forming a gate insulation film on said gate electrode layer and gate electrode material layer; (C) forming a channel layer having a gate electrode layer as a plane surface on the gate insulation film; (D) forming a source/drain electrode layer connected to an ohmic contact layer and for forming a source/drain electrode material layer from the same material as the source/drain electrode layer in a predetermined region on said insulation film; (E) forming a protective film for covering said source electrode layer, said drain electrode layer and said gate electrode material layer; (F) forming a first aperture wherein a part of said gate insulation film and the overlapping layer of the protective film on the gate electrode layer and said gate electrode material layer are selectively etched for exposing a portion of a surface of one of the gate electrode layer and the gate electrode material layer and at the same times, forming a second aperture wherein a portion of the protective film on the source/drain electrode layer and source/drain electrode material layer are selectively etched for exposing a portion of a surface of one of the source/drain electrode layer and the source/drain electrode material layer; and (G) connecting an electrically conductive material layer to at least one of the gate electrode layer, the gate electrode material layer, the source/drain electrode layer and the source/drain electrode material layer through said first aperture and said second aperture.
 12. The method of manufacturing an active matrix substrate in claim 11, wherein: a thin film transistor (TFT) is connected to a scanning line and a signal line; a pixel electrode is connected to the thin film transistor; and a diode for preventing electrostatic destruction constructed for connecting a thin film transistor gate electrode layer and the source/drain electrode layer, on the active matrix substrate.
 13. The method of manufacturing an active matrix substrate in claim 12, wherein the layer formed from the same layer as the pixel electrode is the electrically conductive material layer.
 14. The method of manufacturing an active matrix substrate in claim 11, wherein ITO (Indium Tin Oxide) is the electrically conductive material layer.
 15. A method for peventing preventing electrostatic destruction of active elements in an active matrix liquid crystal display device, comprising the steps of: forming a pixel part including a thin film transistor connected to a scanning line and a signal line arranged in a matrix, and a pixel electrode connected to one end of the thin film transistor; providing protective means for preventing electrostatic destruction, including a diode having a gate electrode layer in the thin film transistor connected to a source/drain electrode layer; and connecting the protective means for preventing static electricity destruction between at least one of said scanning line, said signal line, a member electrically equivalent to at least one of said scanning line and said signal line, and a common electric potential line.
 16. A method of manufacturing a thin film element, comprising the steps of: (A) forming a gate electrode layer and a gate electrode material layer, which is formed of substantially the same material as said gate electrode layer, above a substrate; (B) forming a gate insulation film, a channel layer and an ohmic contact layer above said gate electrode layer and said gate electrode material layer; (C) forming a source electrode layer and a drain electrode layer that are connected to said ohmic contact layer; (D) removing said ohmic contact layer from a region between said source electrode layer and said drain electrode layer by etching; (E) forming a protective film for covering said source electrode layer, said drain electrode layer and said gate electrode material layer, the protective film being in contact with the channel layer in at least a region between said source electrode layer and said drain electrode layer; (F) forming a first aperture wherein a part of said gate insulation film and said protective film above said gate electrode material layer is selectively etched for exposing a portion of a surface of said gate electrode material layer, and substantially simultaneously, forming a second aperture wherein a part of the protective film on said source electrode layer and said drain electrode layer is selectively etched for exposing a portion of a surface of at least one of said source electrode layer and said drain electrode layer; and (G) forming an electrically conductive material layer on at least one of said first aperture and said second aperture.
 17. The method of manufacturing a thin film element in claim 16, wherein said electrically conductive material layer of said second aperture is a pixel electrode.
 18. The method of manufacturing a thin film element in claim 16, wherein said electrically conductive material layer is made of ITO.
 19. The method of manufacturing a thin film element in claim 16, wherein said electrically conductive material layer of said first aperture is an external connection terminal.
 20. The method of manufacturing a thin film element in claim 16, wherein said electrically conductive material layer formed on said second aperture is connected to an electrically conductive material layer formed on said first aperture.
 21. The method of manufacturing a thin film element in claim 16, wherein the gate electrode layer and the gate electrode material layer are formed on one or more layers of the substrate.
 22. A method of manufacturing a thin film element, comprising the steps of: (A) forming a pixel gate electrode layer and a protective element gate electrode layer, which is formed of substantially the same material as said pixel gate electrode layer, above a substrate; (B) forming a gate insulation film, a channel layer and an ohmic contact layer on said pixel gate electrode layer and said protective element gate electrode layer; (C) forming a pixel source electrode layer, a pixel drain electrode layer, a protective element source electrode layer and a protective element drain electrode layer that are connected to said ohmic contact layer; (D) removing said ohmic contact layer from a region between said pixel source electrode layer and said pixel drain electrode layer and from a region between said protective element source electrode layer and said protective element drain electrode layer by etching; (E) forming a protective film for covering said pixel source electrode layer, said pixel drain electrode layer, said protective element source electrode layer and said protective element drain electrode layer, the protective film being in contact with the channel layer in at least a region between said pixel source electrode layer and said pixel drain electrode layer; (F) forming a first aperture wherein a part of said protective film on said pixel source electrode layer and said pixel drain electrode layer is selectively etched for exposing a portion of a surface of at least one of said pixel source electrode layer and said pixel drain electrode layer, and substantially simultaneously, forming a second aperture wherein a part of the protective film on said protective element source electrode layer, said protective element drain electrode layer and said protective element gate electrode layer is selectively etched for exposing a portion of a surface of at least one of said protective element source electrode layer, said protective element drain electrode layer and said protective element gate electrode layer; and (G) forming an electrically conductive material layer on at least one of said first aperture and said second aperture.
 23. The method of manufacturing a thin film element in claim 22, wherein said electrically conductive material layer formed on said second aperture is connected to said electrically conductive material layer formed on said first aperture.
 24. A method of manufacturing an active matrix substrate, comprising the steps of: (A) forming a gate electrode layer and a gate electrode material layer, which is formed of substantially the same material as said gate electrode layer, above a substrate; (B) forming a gate insulation film on said gate electrode layer and said gate electrode material layer; (C) forming a channel layer such that the gate insulation film is disposed between the channel layer and the gate electrode layer; (D) forming a source electrode layer and a drain electrode layer that are electrically connected to said channel layer; (E) forming a protective film for covering said source electrode layer, said drain electrode layer and said gate electrode material layer, the protective film being in contact with the channel layer in at least a region between said source electrode layer and said drain electrode layer; (F) forming a first aperture wherein a part of said gate insulation film and said protective film above said gate electrode material layer is selectively etched for exposing a portion of a surface of said gate electrode material layer, and substantially simultaneously, forming a second aperture wherein a part of said protective film on said source electrode layer and said drain electrode layer is selectively etched for exposing a portion of a surface of at least one of said source electrode layer and said drain electrode layer; and (G) forming an electrically conductive material film on at least one of said first aperture and said second aperture.
 25. The method of manufacturing an active matrix substrate in claim 24, wherein said electrically conductive material layer of said second aperture is a pixel electrode.
 26. The method of manufacturing an active matrix substrate in claim 24, wherein said electrically conductive material layer is made of ITO.
 27. The method of manufacturing an active matrix substrate in claim 24, wherein said electrically conductive material layer of said first aperture is an external connection terminal.
 28. The method of manufacturing an active matrix substrate in claim 24, wherein said electrically conductive material layer formed on said second aperture is connected to an electrically conductive material layer formed on said first aperture.
 29. A method of manufacturing an active matrix substrate, comprising the steps of: (A) forming a pixel gate electrode layer and a protective element gate electrode layer, which is formed of substantially the same material as said pixel gate electrode layer, above a substrate; (B) forming a gate insulation film on said pixel gate electrode layer and said protective element gate electrode material layer; (C) forming a channel layer such that the gate insulation film is disposed between the channel layer and said pixel gate electrode layer, the gate insulation film also being disposed between the channel layer and said protective element gate electrode layer; (D) forming a pixel source electrode layer, a pixel drain electrode layer, a protective element source electrode layer and a protective element drain electrode layer that are electrically connected to said channel layer; (E) forming a protective film for covering said pixel source electrode layer, said pixel drain electrode layer, said protective element source electrode layer and said protective element drain electrode layer, the protective film being in contact with the channel layer in at least a region between said pixel source electrode layer and said pixel drain electrode layer; (F) forming a first aperture wherein a part of said protective film on said pixel source electrode layer and said pixel drain electrode layer is selectively etched for exposing a portion of a surface of at least one of said pixel source electrode layer and said pixel drain electrode layer, and substantially simultaneously, forming a second aperture wherein a part of the protective film on said protective element source electrode layer, said protective element drain electrode layer and said protective element gate electrode layer is selectively etched for exposing a portion of a surface of at least one of the protective element source electrode layer, said protective element drain electrode layer and said protective element gate electrode layer; and (G) forming an electrically conductive material layer on at least one of said first aperture and said second so aperture.
 30. The method of manufacturing an active matrix substrate in claim 29, wherein said electrically conductive material layer formed on said second aperture is connected to said electrically conductive material layer formed on said first aperture.
 31. A method of manufacturing a thin film element, comprising the steps of: (A) forming a gate electrode layer and a gate electrode material layer, which is formed of substantially the same material as said gate electrode layer, above a substrate; (B) forming a gate insulation film, a channel layer and an ohmic contact layer above said gate electrode layer and said gate electrode material layer; (C) forming a source electrode layer and a drain electrode layer that are connected to said ohmic contact layer; (D) removing said ohmic contact layer from a region between said source electrode layer and said drain electrode layer by etching; (E) forming a protective film for covering said source electrode layer, said drain electrode layer and said gate electrode material layer, the protective film being in contact with the channel layer in at least a region between said source electrode layer and said drain electrode layer; (F) forming a first aperture wherein a part of said gate insulation film and said protective film above said gate electrode material layer is selectively etched for exposing a portion of a surface of said gate electrode material layer, and substantially simultaneously, forming a second aperture wherein a part of the protective film over said source electrode layer and said drain electrode layer is selectively etched for exposing a portion of a surface of at least one of said source electrode layer and said drain electrode layer; and (G) forming an electrically conductive material layer on at least one of said first aperture and said second aperture.
 32. An active matrix substrate comprising: a switching element disposed in correspondence with an intersection of a signal line and a scanning line, and a pixel electrode disposed in correspondence with the switching element; a static destructive protection element using thin film transistors established between at least one of the scanning line and said signal line, or a region electrically equivalent to the at least one of the scanning line and the signal line, and a common electric potential region, the static destructive protection element including a diode wherein a gate electrode layer in the thin film transistor, a source electrode layer and a drain electrode layer are connected; and a first aperture formed by selectively removing an insulation layer above the gate electrode layer and a second aperture formed by selectively removing an insulating layer above the source electrode layer and the drain electrode layer; wherein the gate electrode layer, the source electrode layer and the drain electrode layer are electrically connected via the first aperture and the second aperture by an electrically conductive material layer composed of the same material as said pixel electrode.
 33. A method of manufacturing a thin film element, comprising the steps of: (A) forming a gate electrode layer and a gate electrode material layer, which is formed of substantially the same material as said gate electrode layer; (B) forming a gate insulation film, a channel layer and an ohmic contact layer above said gate electrode layer and said gate electrode material layer; (C) forming a source electrode layer and a drain electrode layer that are connected to said ohmic contact layer; (D) removing said ohmic contact layer from a region between said source electrode layer and said drain electrode layer by etching; (E) forming a protective film for covering said source electrode layer, said drain electrode layer and said gate electrode material layer, the protective film being in contact with the channel layer in at least a region between said source electrode layer and said drain electrode layer; (F) forming a first aperture wherein a part of said gate insulation film and said protective film above said gate electrode material layer is selectively etched for exposing a portion of a surface of said gate electrode material layer, and substantially simultaneously, forming a second aperture wherein a part of the protective film on said source electrode layer and said drain electrode layer is selectively etched for exposing a portion of a surface of at least one of said source electrode layer and said drain electrode layer; and (G) forming an electrically conductive material layer on at least one of said first aperture and said second aperture. 